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? motorola 2003 this document contains information on a new product. specifications and information herein are subject to change without notic e. motorola semiconductor technical data mc9s12h-familypp rev 5.5, 11-mar-03 mc9s12h-family product proposal 16-bit microcontroller all mc9s12h-family member microcontroller units (mcu) are 16-bit devices composed of standard on- chip peripherals including a 16-bit central processing unit (cpu12), up to 256k bytes of flash eeprom, 12k bytes of ram, 4k bytes of eeprom, one or two asynchronous serial communications interfaces (sci), a serial peripheral interface (spi), an iic-bus interface (iic), an 8-channel 16-bit timer (tim), a 16-channel, 10-bit analog-to-digital converter (adc), up to six-channel pulse width modulator (pwm), and up to two can 2.0 a, b software compatible modules (mscan12). in addition, they feature a 28x4 or 32x4 liquid crystal display (lcd) controller/driver and a motor pulse width modulator (pwm) consisting of 24 high current outputs suited to drive up to 6 stepper motors. system resource mapping, clock generation, interrupt control, and bus interfacing are managed by the system integration module. the mc9s12h-family has full 16-bit data paths throughout. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. in addition to the i/o ports available in each module, up to 14 i/o ports are available with key-wake-up capability from stop or wait mode. features note: not all features listed here are available in all configurations! ? 16-bit cpu12 upward compatible with m68hc11 instruction set interrupt stacking and programmers model identical to m68hc11 instruction queue enhanced indexed addressing ? 8-bit and 4-bit ports with key wake-up interrupt digital filtering programmable rising or falling edge trigger ? memory options 128k, 256k flash eeprom 2k, 4k byte eeprom 6k, 12k byte ram ? analog-to-digital converter 8 or 16 channels, 10-bit resolution external conversion trigger capability ? one or two 1m bit per second, can 2.0 a, b software compatible modules five receive and three transmit buffers flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit four separate interrupt channels for rx, tx, error and wake-up low-pass filter wake-up function loop-back for self test operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 2 mc9s12h-family product proposal, rev 5.5, 11-mar-03 ? timer 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels two 8-bit or one 16-bit pulse accumulators ? 2 or 6 pwm channels depending on the package option programmable period and duty cycle 8-bit 6-channel or 16-bit 3-channel 8-bit 2 channel or 16-bit 1 channel separate control for each pulse width and duty cycle center-aligned or left-aligned outputs programmable clock select logic with a wide range of frequencies ? serial interfaces one or two asynchronous serial communications interfaces (sci) synchronous serial peripheral interface (spi) inter-integrated circuit interface (iic) 144lqfp ? liquid crystal display driver with variable input voltage configurable for up to 32 frontplanes and 4 backplanes or general purpose input or output 5 modes of operation allow for different display sizes to meet application requirements unused frontplane and backplane pins can be used as general purpose i/o ? 24 high current drivers suited for pwm motor control 12 pwm channels with common frequency timebase each pwm channel switchable between two drivers in an h-bridge configuration left, right and center aligned outputs support for sin and cos drive dithering output slew rate limitation ? sim (system integration module) crg (windowed cop watchdog, real time interrupt, clock monitor, clock generation and reset) mebi (multiplexed external bus interface) mmc (memory map and interface) int (interrupt control) bkp (breakpoints) bdm (background debug mode) ? clock generation phase-locked loop clock frequency multiplier self clock mode in absence of external clock low power 0.5 to 16mhz crystal oscillator reference clock ? 144-pin or 112-pin qfp package i/o lines with 5v input and drive capability 5v a/d converter inputs operation at 32mhz equivalent to 16mhz bus speed development support single-wire background debug? mode (bdm) on-chip hardware breakpoints f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12h-family product proposal, rev 5.5, 11-mar-03 motorola 3 ? pin out explanations: a/d is the number of a/d channels. motor denotes the number of high current drive pins/number of stepper motors which can be driven i/o is the sum of ports capable to act as digital input or output. 144 pin packages: port a = 8, b = 8, e = 6 + 2 input only, h = 8, j = 4, k = 5, l=8, m = 6, p = 6, s = 8, t = 8, pad = 16 input only. 14 inputs provide interrupt capability (h = 8, j = 4, irq, xirq) 112 pin packages: port a = 8, b = 8, e = 6 + 2 input only, k=5, l=4, m = 4, p = 2, s = 6, t = 8, pad = 8 input only. 2 inputs provide interrupt capability (irq, xirq) table 1 list of mc9s12h-family members flash ram eeprom package device can sci spi iic a/d pwm lcd motor i/o 256k 12k 4k 144lqfph256 221116632x424/693 112lqfph256 21108228x424/661 128k 6k 2k 112lqfp h128 21108228x424/661 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 4 mc9s12h-family product proposal, rev 5.5, 11-mar-03 extal xtal bkgd xirq periodic interrupt cop watchdog clock monitor breakpoints pll xfc irq eclk pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 test pb4 pb0 pb7 pb6 fp4 fp3 fp2 fp1 fp0 fp7 fp6 pe4 pe5 pe6 pe0 pe1 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 rxd txd sdi/miso sdo/mosi ps4 ps5 ps0 ps1 pulse width modulator pw2 pw0 pw1 pw3 pw4 pw5 pp3 pp4 pp5 pp0 pp1 pp2 pk3 pk7 pk0 pk1 sck ss ps6 ps7 spi rxcan txcan pm2 pm3 pin kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ddra ddrb pta ptb ddre pte ptk ddrk ptp ddrp pts ddrs ptm ddrm ddrh pth pk2 interrupt logic fp12 fp11 fp10 fp9 fp8 fp15 fp14 bp0 bp1 bp2 bp3 fp23 pl3 pl2 pl1 pl0 ddrl ptl fp19 fp18 fp17 fp16 pe7 pe3 pte ddre pe2 fp22 fp21 fp20 vlcd vlcd m0c0m m0c0p pu0 pu1 ptu ddru pwm0 motor0 lcd sci0 can0 ph2 modb moda figure 1. mc9s12h-family block diagram reset vddpll vsspll cpu12 clock and reset generation module ptk ddrk fp13 pb5 pb3 pb2 pb1 fp5 pix0 pix1 pix2 pix3 addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 addr15 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 ptt ddrt fp24 fp25 fp26 fp27 an02 an06 an00 an07 an01 an03 an04 an05 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 vrh vrl an10 an14 an08 an15 an09 an11 an12 an13 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa analog to digital converter ptad vrh vrl vdda vssa kwj2 kwj0 kwj1 kwj3 pj3 pj0 pj1 ddrj ptj pj2 128k, 256k bytes flash eeprom 2k, 4k bytes eeprom 4k, 6k, 12k bytes ram multiplexed address/data bus ppage data15 motor0 and motor1 supply vddm1 vssm1 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 multiplexed wide bus multiplexed narrow bus ecs /romone xaddr14 xaddr15 xaddr16 xaddr17 noacc/xclks lstrb /taglo r/w vddr vdd1 vss1,2 voltage regulator input capture and output compare timer scl sda pm0 pm1 iic vddx1,2 vssx1,2 vsspll pll 2.5v i/o driver 5v a/d converter 5v & vddpll vdd1 vss1,2 internal logic 2.5v vdda vssa vddr vreg input 5v supply pins driver note: not all functionality shown in this block diagram is available in all versions! pl7 pl6 pl5 pl4 fp31 fp30 fp29 fp28 voltage regulator reference system integration module single-wire background debug module rxd txd ps2 ps3 sci1 rxcan txcan pm4 pm5 can1 m0c1m m0c1p pu2 pu3 pwm1 m1c0m m1c0p pu4 pu5 pwm2 motor1 m1c1m m1c1p pu6 pu7 pwm3 m2c0m m2c0p pv0 pv1 ptv ddrv pwm4 motor2 motor2 and motor3 supply vddm2 vssm2 m2c1m m0c1p pv2 pv3 pwm5 m3c0m m3c0p pv4 pv5 pwm6 motor3 m3c1m m3c1p pv6 pv7 pwm7 m4c0m m4c0p pw0 pw1 ptw ddrw pwm8 motor4 motor4 and motor5 supply vddm3 vssm2 m4c1m m4c1p pw2 pw3 pwm9 m5c0m m5c0p pw4 pw5 pwm10 motor5 m5c1m m5c1p pw6 pw7 pwm11 pins shown in bold are not available in the 112 qfp package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12h-family product proposal, rev 5.5, 11-mar-03 motorola 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 mc9s12h-family 112 qfp 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 vssx1 vddx1 pk7/ecs /romone/fp23 pe7/noacc/xclks/fp22 pe3/lstrb /taglo /fp21 pe2/r/w /fp20 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vdda vrh vrl vssa pe0/xirq pe4/eclk pe6/modb m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 rxd0/ps0 txd0/ps1 vss2 vddr vddx2 vssx2 bkgd reset vddpll xfc vsspll extal xtal test rxcan0/pm2 txcan0/pm3 rxcan1/pm4 txcan1/pm5 moda/pe5 miso/ps4 mosi/ps5 sck/ps6 ss /ps7 irq /pe1 figure 2. mc9s12h-family pin assignments, 112 pin qfp package can1 is not available on the mc9s12h64 version! pm5:4 will be general purpose i/o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 6 mc9s12h-family product proposal, rev 5.5, 11-mar-03 m0c0m/pu0 m0c0p/pu1 m0c1m/pu2 m0c1p/pu3 vddm1 vssm1 m1c0m/pu4 m1c0p/pu5 m1c1m/pu6 m1c1p/pu7 kwh0/ph0 kwh1/ph1 kwh2/ph2 kwh3/ph3 m2c0m/pv0 m2c0p/pv1 m2c1m/pv2 m2c1p/pv3 vddm2 vssm2 m3c0m/pv4 m3c0p/pv5 m3c1m/pv6 m3c1p/pv7 kwh4/ph4 kwh5/ph5 kwh6/ph6 kwh7/ph7 m4c0m/pw0 m4c0p/pw1 m4c1m/pw2 m4c1p/pw3 vddm3 vssm3 m5c0m/pw4 m5c0p/pw5 m5c1m/pw6 m5c1p/pw7 pwm0/pp0 pwm1/pp1 pwm2/pp2 pwm3/pp3 pwm4/pp4 pwm5/pp5 rxd0/ps0 txd0/ps1 rxd1/ps2 txd1/ps3 vss2 vddr vddx2 vssx2 modc/taghi /bkgd reset vddpll xfc vsspll extal xtal test sda/pm0 scl/pm1 rxcan0/pm2 txcan0/pm3 rxcan1pm4 txcan1/pm5 moda/ipipe0/pe5 miso/ps4 mosi/ps5 sck/ps6 ss /ps7 irq /pe1 pb5/addr5/data5/fp5 pb4/addr4/data4/fp4 pb3/addr3/data3/fp3 pb2/addr2/data2/fp2 pb1/addr1/data1/fp1 pb0/addr0/data0/fp0 pk0/xaddr14/bp0 pk1/xaddr15/bp1 pk2/xaddr16/bp2 pk3/xaddr17/bp3 vlcd vss1 vdd1 pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vdda vrh vrl vssa pe0/xirq pe4/eclk pe6/ipipe1/modb pt7/ioc7 pt6/ioc6 pt5/ioc5 pt4/ioc4 pt3/ioc3/fp27 pt2/ioc2/fp26 pt1/ioc1/fp25 pt0/ioc0/fp24 pj3/kwj3 pj2/kwj2 pj1/kwj1 pj0/kwj0 vssx1 vddx1 pk7/ecs /romone/fp23 pe7/noacc/xclks/fp22 pe3/lstrb /taglo/ fp21 pe2/r/w /fp20 pl7/fp31 pl6/fp30 pl5/fp29 pl4/fp28 pl3/fp19 pl2/fp18 pl1/fp17 pl0/fp16 pa7/addr15/data15/fp15 pa6/addr14/data14/fp14 pa5/addr13/data13/fp13 pa4/addr12/data12/fp12 pa3/addr11/data11/fp11 pa2/addr10/data10/fp10 pa1/addr9/data9/fp9 pa0/addr8/data8/fp8 pb7/addr7/data7/fp7 pb6/addr6/data6/fp6 mc9s12h-family 144 qfp pins shown in bold are not available in the 112 qfp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 figure 3. mc9s12h-family pin assignments, 144 pin qfp package f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12h-family product proposal, rev 5.5, 11-mar-03 motorola 7 table 1. pin descriptions note: features shown in bold are not available in the 112 pin qfp package. pin name function 1 pin name function 2 pin name function 3 description pu[3:0] m0c0m, m0c0p, m0c1m, m0c1p ? function 1: general purpose input/output pins. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive current flow through coil 0 when m0c0p is driven to a logic high state. pwm output on m0c1m results in a positive current flow through coil 1 when m0c1p is driven to a logic high state. vddm1, vssm1 ?? supply input pins for motor 0 and motor 1 output drivers. tolerance = 5 v 10%. pu[7:4] m1c0m, m1c0p, m1c1m, m1c1p ? function 1: general purpose input or output pin. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive current flow through coil 0 when m1c0p is driven to a logic high state. pwm output on m1c1m results in a positive current flow through coil 1 when m1c1p is driven to a logic high state. ph[3:0] kwh[3:0] ? function 1: general purpose input or output pin. function 2: key wake-up interrupt pin. when configured as an in- put, can generate an interrupt causing the mcu to exit stop or wait mode. pv[3:0] m2c0m, m2c0p, m2c1m, m2c1p ? function 1: general purpose input or output pin. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive current flow through coil 0 when m2c0p is driven to a logic high state. pwm output on m2c1m results in a positive current flow through coil 1 when m2c1p is driven to a logic high state. vddm2, vssm2 ?? supply input pins for motor 2 and motor 3 output drivers. tolerance = 5 v 10%. pv[7:4] m3c0m, m3c0p, m3c1m, m3c1p ? function 1: general purpose input or output pin. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive current flow through coil 0 when m3c0p is driven to a logic high state. pwm output on m3c1m results in a positive current flow through coil 1 when m3c1p is driven to a logic high state. ph[7:4] kwh[7:4] ? function 1: general purpose input or output pin. function 2: key wake-up interrupt pin. when configured as an in- put, can generate an interrupt causing the mcu to exit stop or wait mode. pw[3:0] m4c0m, m4c0p, m4c1m, m4c1p ? function 1: general purpose input or output pin. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c0m results in a positive current flow through coil 0 when m4c0p is driven to a logic high state. pwm output on m4c1m results in a positive current flow through coil 1 when m4c1p is driven to a logic high state. vddm3, vssm3 ?? supply input pins for motor 4 and motor 5 output drivers. tolerance = 5 v 10% pw[7:4] m5c0m, m5c0p, m5c1m, m5c1p ? function 1: general purpose input or output pin. function 2: high current pwm output pins which can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c0m results in a positive current flow through coil 0 when m5c0p is driven to a logic high state. pwm output on m5c1m results in a positive current flow through coil 1 when m5c1p is driven to a logic high state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 8 mc9s12h-family product proposal, rev 5.5, 11-mar-03 pp[1:0] pwm[1:0] ? function 1: general purpose input or output pin. function 2: pulse width modulator (pwm) channel output pin. pp[5:2] pwm[5:2] ? function 1: general purpose input or output pin. function 2: pulse width modulator (pwm) channel output pin. ps[1:0] txd0, rxd0 ? function 1: general purpose input or output pin. function 2: rxd0 is the receive pin and txd0 is the transmit pin of serial communication interface 0 (sci0). ps[3:2] txd1, rxd1 ? function 1: general purpose input or output pin. function 2: rxd1 is the receive pin and txd1 is the transmit pin of serial communication interface 1(sci1). vss2 ?? core ground. vddr ?? power supply input pin for voltage regulator. nominal 5v bkgd taghi modc function 1: pseudo-open-drain communication pin for the background debug function. function 2: in mcu expanded modes of operation when instruction tag- ging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. function 3: at the rising edge during reset, the state of this pin is latched to the modc bit to set the mcu operating mode. reset ?? an active low bidirectional control signal, it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. vddpll, vsspll ?? pll supply output pins. no load allowed except for bypass capacitors. xfc ?? dedicated pin used to create the pll loop filter. extal, xtal ?? crystal driver and external clock input pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. test ?? pin reserved for test. pm[1:0] scl, sda ? function 1: general purpose input or output pin. function 2: sda is the serial data pin and scl is the serial clock pin for the inter-ic bus interface (iic). pm[3:2] txcan0, rxcan0 ? function 1: general purpose input or output pin. function 2: rxcan0 is the receive pin and txcan0 is the transmit pin for the motorola scalable controller area network controller 0 (mscan0). pm[5:4] txcan1, rxcan1 ? function 1: general purpose input or output pin. function 2: rxcan1 is the receive pin and txcan1 is the transmit pin for the motorola scalable controller area network controller 1 (mscan1). can1 is not available for the mc9s12h64 version! pe[6:5] modb, moda ipipe1, ipipe0 function 1: general purpose input or output pin. function 2: the state of the moda and modb pins during reset deter- mine the initial operating mode of the mcu. function 3: instruction queue tracking signals. ps4 miso ? function 1: general purpose input or output pin. function 2: master input (during master mode) or slave output (during slave mode) pin for the serial peripheral interface (spi). table 1. pin descriptions note: features shown in bold are not available in the 112 pin qfp package. pin name function 1 pin name function 2 pin name function 3 description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12h-family product proposal, rev 5.5, 11-mar-03 motorola 9 ps5 mosi ? function 1: general purpose input or output pin. function 2: master output (during master mode) or slave input (during slave mode) pin for the serial peripheral interface (spi). ps6 sck ? function 1: general purpose input or output pin. function 2: serial clock pin for the serial peripheral interface (spi). ps7 ss ? function 1: general purpose input or output pin. function 2: slave select pin for the serial peripheral interface (spi). pe1 irq ? function 1: general purpose input pin. function 2: maskable interrupt request input provides a means of apply- ing asynchronous interrupt requests. will wake up the mcu from stop or wait mode. pe4 eclk ? function 1: general purpose input or output pin. function 2: eclk is the internal bus clock output. eclk can be used as a timing reference. pe0 xirq ? function 1: general purpose input pin. function 2: nonmaskable interrupt request input provides a means of applying asynchronous interrupt requests. will wake up the mcu from stop or wait mode. vrh, vrl ?? reference voltage input pins for the analog to digital converter. vdda, vssa ?? supply input pins for the voltage regulator and the analog to digital con- verter. tolerance = 5v 5%. pad[07:00] an[07:00] ? function 1: general purpose input pin. function 2: analog inputs for the analog to digital converter. pad[15:08] an[15:08] ? function 1: general purpose input pin. function 2: analog inputs for the analog to digital converter. v dd1 , v ss1 ?? core supply output pins. no load allowed except for bypass capacitors. v lcd ?? supply input pin for the lcd driver. adjusting the voltage on this pin will change the display contrast. pk[3:0] bp[3:0] xaddr[17:14] function 1: general purpose input or output pin. function 2: lcd backplane segment driver output pin. function 3: in mcu expanded modes of operation, expanded address pins for the external bus. pb[7:0] fp[7:0] addr[7:0]/ data[7:0] function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. pa[7:0] fp[15:8] addr[15:8]/ data[15:8] function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. pl[3:0] fp[19:16] ? function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. pl[7:4] fp[31:28] ? function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. pe2 fp20 r/w function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operations, performs the read/ write output signal for the external bus. this pin indicates direction of data on the external bus. table 1. pin descriptions note: features shown in bold are not available in the 112 pin qfp package. pin name function 1 pin name function 2 pin name function 3 description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 10 mc9s12h-family product proposal, rev 5.5, 11-mar-03 pe3 fp21 lstrb / taglo function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: in mcu expanded modes of operation, lstrb is used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, taglo is used to tag the low half of the in- struction word being read into the instruction queue. pe7 fp22 noacc/ xclks function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: the xclks signal selects between an external clock or os- cillator configuration during reset. this pin should be at a logic high dur- ing reset if an external clock is used on the extal input pin. this pin should be at a logic low during reset if an oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-down device during reset, if the pin is left floating, the default configuration is an os- cillator circuit on extal and xtal. during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or free cycle. this signal will assert when the cpu is not using the bus. pk7 fp23 ecs / romone function 1: general purpose input or output pin. function 2: lcd frontplane segment driver output pin. function 3: during mcu expanded modes of operation, this pin is used to enable the flash eeprom memory in the memory map (romone). also during mcu expanded modes of operation, this pin is used as the emulation chip select signal (ecs ). vddx1,2, vssx1,2 ?? supply input pins for input/output drivers. tolerance = 5v 5%. pj[3:0] kwj[3:0] ? function 1: general purpose input or output pin. function 2: key wake-up interrupt pin. when configured as an in- put, can generate an interrupt causing the mcu to exit stop or wait mode. pt[3:0] ioc[3:0] fp[27:24] function 1: general purpose input or output pin. function 2: timer system input capture or output compare pin. function 3: lcd frontplane segment driver output pin. pt[7:4] ioc[7:4] ? function 1: general purpose input or output pin. function 2: timer system input capture or output compare pin. table 1. pin descriptions note: features shown in bold are not available in the 112 pin qfp package. pin name function 1 pin name function 2 pin name function 3 description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc9s12h-family product proposal, rev 5.5, 11-mar-03 motorola 11 figure 4. mc9s12h256 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window sixteen * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $1000 $3fff $0000 $0fff 4k bytes eeprom mappable to any 4k boundary $0000 $03ff 1k register space mappable to any 2k boundary mappable to any 16k boundary 12k bytes ram alignable to top ($1000 - $3fff) or bottom ($0000 - $2fff) initially overlapped by register space f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola 12 mc9s12h-family product proposal, rev 5.5, 11-mar-03 figure 5. mc9s12h128 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $0800 $1000 $2800 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window eight * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $2800 $3fff 6k bytes ram mappable to any 8k boundary $0800 $0fff 2k bytes eeprom mappable to any 2k boundary $0000 $03ff 1k register space mappable to any 2k boundary alignable to top ($2800 - $3fff) or bottom ($2000 - $37ff) of 8k boundary the figure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0800 - $1fff: 6k ram $0000 - $07ff: 2k eeprom (1k not visible) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters can and do vary in different applications. all operating parameters, including typicals must be validate d for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of oth ers. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or othe r applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a s ituation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims , costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver colorado 80217. 1-800-441-2447, (303) 675-2140 internet: http://mcu.motsps.com japan: motorola japan ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 81-3-3521-8315 asia pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 figure 6. mc9s12h64 user configurable memory map $0000 $ffff $c000 $8000 $4000 $0400 $0800 $2000 $3000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window four * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $0800 $0fff 1k bytes eeprom mappable to any 2k boundary $0000 $03ff 1k register space mappable to any 2k boundary $3000 $3fff 4k bytes ram the figure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $0fff: 4k ram (1k not visible) $0000 - $07ff: 1k eeprom (repeated twice in 2k address space, not visible) $1000 - $3fff: 12k flash repeated twice in 2k space mappable to any 4k boundary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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